1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a precharging circuit and a semiconductor memory device including the same.
2. Description of the Related Art
In general, a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) device uses various input/output line pairs to write data in a core region or read data stored in the core region. Among input/output line pairs, a local input/output line pair is precharged before the performance of a next write operation or a next read operation because the input/output lines have different voltage levels after the performance of a read operation or a write operation. Further, in performing a burst operation function, where reading or writing data is performed two or more times consecutively, a semiconductor memory device precharges the local input/output line pair between the data processing operations.
FIG. 1 is a diagram illustrating a structure of a semiconductor memory device including a conventional precharging circuit.
Referring to FIG. 1, a semiconductor memory device 100 includes a write driver 110 configured to transmit data, loaded on a global input/output line GIO, to a local input/output line pair LIO/LIOB in a write operation mode, a read driver 120 configured to transmit data, loaded on the local input/output line pair LIO/LIOB, to the global input/output line GIO in a read operation mode, a precharging circuit 130 configured to precharge the local input/output line pair LIO/LIOB in response to a precharge control signal LIOPCG, and a core region 140 configured to store data loaded on the local input/output line pair LIO/LIOB in the write operation mode and transmit stored data to the local input/output line pair LIO/LIOB in the read operation mode.
The write driver 110 transmits data, loaded on the global input/output line GIO, to the local input/output line pair LIO/LIOB in response to a write driver strobe signal WSTB. More specifically, the write driver 110 drives the local input/output line pair LIO/LIOB with a desired voltage (e.g., the core voltage VCORE) in response to data transmitted through the global input/output line GIO.
The read driver 120 transmits data, loaded on the local input/output line pair LIO/LIOB, to the global input/output line GIO in response to a read driver strobe signal IOSTB. In general, the read driver 120 includes an input/output sense amplifier (IOSA).
The precharging unit 130 includes first to third PMOS transistors P1, P2 and P3 configured to precharge the local input/output line pair LIO/LIOB to the level of the core voltage VCORE. Herein, the precharge control signal LIOPCG is applied to the gate terminals of the first to third PMOS transistors P1, P2 and P3 after passing through first and second inverters INV1 and INV2. When precharge control signal LIOPCG is activated to a logic low level, the first to third PMOS transistors P1, P2 and P3 are turned on to precharge the local input/output line pair LIO/LIOB to the level of the core voltage VCORE.
The core region 140 includes a bit line sense amplifier (BLSA) and a memory cell array (not illustrated). In a read/write operation mode, the core region 140 transmits data stored in a memory cell to the local input/output line pair LIO/LIOB or store data loaded on the local input/output line pair LIO/LIOB in a memory cell.
Hereinafter, operations of the semiconductor memory device 100 will be described with reference to FIGS. 2A and 2B.
FIG. 2A is a timing diagram illustrating an operation of the semiconductor memory device 100 in a read operation mode. FIG. 2B is a timing diagram illustrating an operation of the semiconductor memory device 100 in a write operation mode.
Referring to FIG. 2A, when a read command RD is inputted in synchronization with a rising edge of a clock signal CLK, data from the core region 140 are loaded on the local input/output line pair LIO/LIOB.
Next, the read driver 120 sequentially amplifies data, loaded on the local input/output line pair LIO/LIOB, in response to the read driver strobe signal IOSTB and transmits the results to the global input/output line GIO. In response to the precharge control signal LIOPCG, the precharging unit 130 precharges the local input/output line pair LIO/LIOB by the core voltage VCORE before the next read operation, that is, between the read commands RD. In this context, data transmitted consecutively from the core region 140 are sequentially amplified by the bit line sense amplifier (BLSA) and are loaded on the local input/output line pair LIO/LIOB. The data amplified by the bit line sense amplifier (BLSA) are transmitted to the local input/output line pair LIO/LIOB as a signal having a smaller voltage swing range than the output of the write driver 110. Therefore, the precharging operation is performed between the read commands RD so that the data consecutively loaded on the local input/output line pair LIO/LIOB are accurately transmitted to the global input/output line GIO.
Referring to FIG. 2B, when a write command WT is inputted in synchronization with a rising edge of the clock signal CLK, the relevant data are loaded on the global input/output line GIO.
Next, the write driver 110 sequentially transmits data, loaded on the global input/output line GIO, to the local input/output line pair LIO/LIOB in response to the write driver strobe signal WSTB. Since the write driver 110 drives the local input/output line pair LIO/LIOB with a sufficiently large driving power, the data loaded on the local input/output line pair LIO/LIOB forms a signal with a large voltage swing range. As in the read operation mode, in response to the precharge control signal LIOPCG, the precharging unit 130 precharges the local input/output line pair LIO/LIOB between the write commands WT.
Here, the conventional semiconductor memory device 100 has the following features.
As described above, the precharging unit 130 performs a precharging operation between the read command RD and the write command WT. However, the read operation mode is to have a precharging operation, but a precharging operation is optional in the write operation mode. More specifically, a precharging operation is to be performed before/after the input of the read command RD for accurate data transmission because data corresponding to a signal with a small voltage swing range is loaded on the local input/output line pair LIO/LIOB, whereas a precharging operation is not necessary in the write operation mode because data of a signal with a large voltage swing range is loaded on the local input/output line pair LIO/LIOB. However, as illustrated in FIG. 2B, in the write operation mode, the precharge control signal LIOPCG is continuously toggled according to the consecutively-inputted write command WT.
Accordingly, the local input/output line pair LIO/LIOB is precharged to the level of the core voltage VCORE whenever the write command WT is inputted and the power consumption due to precharging to the core voltage VCORE in the consecutive write operations unnecessarily occurs. Also, since the precharge operation is performed whenever the write command WT is inputted, the write driver 110 pulls down the local input/output line pair LIO/LIOB precharged to the level of the core voltage VCORE, thus cause unnecessary power consumption in the write driver 110.